As is well known, a non-volatile memory is able to continuously retain data after the supplied power is interrupted. Generally, after the non-volatile memory leaves the factory, the user may program the non-volatile memory in order to record data into the memory cells of the non-volatile memory.
According to the number of times the non-volatile memory is programmed, the non-volatile memory cells may be classified into several types, including multi-time programmable memory cells (also referred as MTP memory cells), one time programmable memory cells (also referred as OTP memory cells) and mask read-only memory cells (also referred as Mask ROM memory cells).
Generally, the stored data of the MTP memory cell may be modified many times. On the contrary, the OTP memory cell may be programmed once. After the OTP memory cell is programmed, the stored data cannot be modified. After the mask read-only memory cells leaves the factory, all stored data have been recorded therein. The user is only able to read the stored data from the mask read-only memory cells, but is unable to program the mask read-only memory cells.
Moreover, the memory cell of the non-volatile memory can be programmed to at least two storage states. For example, the memory cell in the first storage state generates a lower cell current, and the memory cell in the second storage state generates a higher cell current. While a read action is performed, a sensing circuit judges the storage state of the memory cell according to the magnitude of the cell current. Generally, the first storage state is referred as an erased state, and the second storage state is referred as a programmed state.
FIG. 1A is a schematic circuit diagram illustrating a sensing circuit for a conventional non-volatile memory. FIG. 1B is a schematic timing diagram illustrating associated signals processed by the sensing circuit of FIG. 1A.
As shown in FIG. 1A, the non-volatile memory 110 comprises plural memory cells cell_1˜cell_n and a select circuit 112. The plural memory cells cell_1˜cell_n are connected with plural input terminals of the select circuit 112. The output terminal of the select circuit 112 is connected with the sensing circuit 120.
Generally, after a control circuit (not shown) determines a selected cell from the non-volatile memory 110, the selected cell is connected with the sensing circuit 120 through the select circuit 112. Consequently, the sensing circuit 120 judges the storage state of the selected cell.
For example, if the memory cell cell_2 is determined as the selected cell while the read action is performed, the memory cell cell_2 generates a cell current Icell. The cell current Icell is transmitted to the sensing circuit 120 through the select circuit 112.
Generally, a parasitic capacitor Cpara such as a bit-line parasitic capacitor is formed between the non-volatile memory 110 and the sensing circuit 120. When the memory cell cell_2 generates the cell current Icell, the cell current Icell will charge the parasitic capacitor Cpara.
Please refer to FIG. 1 B. When the cell current Icell generated by the memory cell cell_2 is outputted from the select circuit 112, a sensing voltage Vsense at the input terminal of the sensing circuit 120 is gradually increased. Consequently, the sensing circuit 120 determines the storage state of the memory cell cell_2 according to the sensing voltage Vsense.
For example, the triggering voltage of the sensing circuit 120 is Vtrig-A. If the memory cell cell_2 is in the first storage state, the cell current Icell generated by the memory cell cell_2 is lower. Consequently, the sensing voltage Vsense cannot be increased quickly. After a response time tra, the sensing voltage Vsense does not reach the triggering voltage Vtrig-A of the sensing circuit 120. Meanwhile, a data signal Data outputted from the sensing circuit 120 has a first logic level (i.e., in a low level state). The low level state of the data signal Data denotes the first storage state of the memory cell cell_2.
If the memory cell cell_2 is in the second storage state, the cell current Icell generated by the memory cell cell_2 is higher. Consequently, the sensing voltage Vsense is increased quickly. After the response time tra, the sensing voltage Vsense reaches the triggering voltage Vtrig-A of the sensing circuit 120. Meanwhile, the data signal Data outputted from the sensing circuit 120 has a second logic level (i.e., in a high level state). The high level state of the data signal Data denotes the second storage state of the memory cell cell_2.
In case that the triggering voltage of the sensing circuit 120 is Vtrig-B, the response time of the sensing circuit 120 is trb. The response time trb is shorter than the response time tra. Since the triggering voltage of the sensing circuit 120 is lower, the response time is shorter. Under this circumstance, the sensing circuit 120 generates the data signal Data more quickly.